Hi,
I am working on a design involving a virtex II -5. I read in a previous post that the skew one could expect from a clock tree is less than 100 ps. However when, on the design I am developping, I run the timing analyzer I get a skew for some clock on a clock tree of about 450 ps or 500 ps (using the 5.1i F23). How should I interpret this difference ? Any clue ? Which figure is the right one ?
J.F. Hasson
J.F.,
The report by the tools is correct.
Different sized parts will have different skews (delays) in the their clock trees due to size.
Additionally, skew is a function of position on the tree, so from the top left corner down to the middle of a part all the way to the bottom left corner, the skew will be less than 130 ps for a 2V6000, wheras from the top left corner over towards the top middle over to the right corner, it will be about 450 ps for a
2V6000.Top to bottom: 130 ps. Right to left: 450 ps. Smallest in the middles, largest at the corners.
For a 2V1000, these are all less than 100 ps.
Thus if you wanted to make the highest speed wide parallel interface, I would use the left or right sides (least skew), rather than the top or bottom edges (for least skew between bits).
If I had to use the top or bottom edges, I would try to group the IOs near the center, or near the left and right extremes.
Again the timing reports and FPGA_Editor report the right (worst case) numbers.
Hope this helps,
Aust> Hi,
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