I'm using WebPACK 6.3.01i. The synthesis report tells me the minimum clock period is about 17 ns.
How do I get the same kind of static timing info after place and route? The P&R report shows max clock delay, net skew, pin delay, etc., but I don't see min period or max frequency. The async delay report says that the max delay is about 6.6 ns; am I supposed to infer a minimum clock period from that?
Thanks, Eric
Thanks, I'll give that a try. It seems somewhat surprising that they don't report the clock period without an explicit constraint; Cypress WARP does.
I am not aware that they *don't* report a max clock speed, but it is very unusual to care about clock speed if you don't spec a requirement. If you don't use a speed constraint, the tool assumes you don't care about the speed and just does a route without any optimization. Isn't that obvious?
Dear Eric,
You can get the clock period in Timing Analyzer by selecting "Against Auto Generated Design Constraints..." whatever you have added the PERIOD constraints or not, even if that is recomanded.
"Eric Smith" ???? news: snipped-for-privacy@ruckus.brouhaha.com...
In
No, it's not obvious. You could just as easily say that an automaker shouldn't include a speedometer in a new car unless you tell the dealer how fast you plan to drive.
If I give an explicit constraint, I want the tools to work harder (if necessary) to try to meet it, but that doesn't mean that if I don't give a constraint that I don't care about it at all. By that reasoning it would be fine for the tools to produce a design with a minimum clock period of a fortnight.
I don't understand your point. If you don't tell the tool what an acceptable clock period is, then how is the tool supposed to know the difference between a nanosecond and a fortnight? Tools are not people, they can't reason. Besides, how would *I* know what you find an acceptable clock period if you don't tell me? I still see systems that are clocked well below 10 MHz.
The tools could at least tell me what the worst case clock-clock time is for each clock. That's not rocket science. And maybe even give a warning for not specifying the appropriate constraints.
Who said the tool does not give you the results? I belive at least one post here said that info *was* available.
I don't expect it to reason. I just expect it to tell me the result.
I never said that 10 MHz was an unacceptable outcome. That has nothing to do with whether the tool should provide me with the result of a static timing analysis.
It was available only after I provided an explicit constraint. It was not obvious that this was what was required to get static timing analysis. If the tools are going to have a test in them somewhere along the lines of "if the user didn't specify a constraint, skip the static timing analysis", then they could at least output a message to that effect to the log.
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