Dear All, So, I've got this design. It has several clocks, all asynchronous to each other. Lets call them Clk1, Clk1 .. ClkN. So, I generate a new clock 'masterclock' from a DCM, and use it to generate clock enables from the clocks, Clk1, Clk1 .. ClkN. The 'masterclock' made in a DCM and is going at a faster rate than each of the clocks. This means I have a nice synchronous design with just masterclock coming from a BUFG. Now the Clk1, Clk1 .. ClkN clocks feed this circuit, copied from a CAF post by Rickman, through the general routing fabric, i.e. no BUFG involved.
|------- Metastable -------| __________ | | _____ |------O| inverter |-------|---------------| | Enable | |__________| | | XOR |---->
| ______ ______ | ______ |--|_____| Out | | | | | | | | | |---| D Q |-----| D Q |--|--| D Q |--| | | | | | | Clk1 | | | | | |
-------|> | ---|> | |---|> | |______| | |______| | |______| | | |___________|___________ Masterclock
I'm keen to keep the delays around the metastable bit of the circuit as short as possible, so I included in my UCF file stuff like this:
NET "masterclock" TNM_NET = "masterclock_FFS_grp"; NET "clk1" TNM_NET = "clk1_FFS_grp"; TIMESPEC TS1 = FROM : clk1_FFS_grp TO masterclock_FFS_grp :
1.350ns; TIMESPEC TS2 = FROM : masterclock_FFS_grp TO clk1_FFS_grp : 1.350ns;and so on for the other clocks upto ClkN.
So far, so good. Then it fails the timing with reports like this in timing analyser:-
Slack: -0.941ns (requirement - (data path - clock path skew + uncertainty)) Source: clock_in_ff (FF) Destination: clock_in_d (FF) Requirement: 1.350ns Data Path Delay: 1.347ns (Levels of Logic = 0) Clock Path Skew: -0.944ns Source Clock: clk1 rising Destination Clock: masterclock rising Clock Uncertainty: 0.000ns
The timing analyser inserts a mystery value for 'Clock Path Skew'. It seems to only do this if the 'Source Clock' comes from a DCM. (In this example Clk1 happened to come from a DCM. I get the same problem with TS2 even if Clk1 comes from outside the device and doesn't go near a DCM.) So, the question is, where does the 'Clock Path Skew' value come from? How can it make up skew between two unrelated clocks? Thanks, Syms.
p.s. The work around is to put MAXDELAY constraints on the nets, but then this doesn't take into account Tcko and Tdick. This design is in several different FPGA families, and I'd like for these timings to be included automatically.