modular design flow in Xilinx ISE 6.1.

Hello All,

I am having problems running the modular design flow in Xilinx ISE


Everything seems OK until I configure (Spartan2 via Boundary Scan /Parallel using Impact) I get a programming failed message - the done pin failed to go high. I have tried a few different options in Bitgen with no success.

Also, the Xilinx ISE 'development systems reference guide' and the Xilinx answers database seem to conflict on the correct use of ngo/ngd files in the modular flow. i.e.

Development Systems Reference Guide, Modular Design Section, Top of Page 93 (PDF version)

“Note: ngdbuild produces two files, design_name.ngd and The file is used during subsequent Modular Design steps, while design_name.ngd is not.”


Xilinx Answer Record # 17058 6.1i Modular Design

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“An NGO file is produced only if an EDIF netlist is used as the input to NGDBuild. The NGC netlist created by XST is already in Xilinx Database Format, and does not need to be converted to an NGO file.”

So could the fact a am using the NGC netlist produced by ngdbuild instead of the ngo file prescribed by the Development Systems Ref Guide be causing this problem??

Please Help (Its nearly Christmas!)

Ian Colwill, University Of Sussex, UK

Reply to
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No. NGC and NGO have essentially the same info, so the NGC can be used in the modular design flow. We'll fix the reference guide to say that NGC and NGO can be used.

I suspect your problem is related to downloading into the FPGA.


Reply to
Steve Lass

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