I am having problems running the modular design flow in Xilinx ISE6.1.
Everything seems OK until I configure (Spartan2 via Boundary Scan /Parallel using Impact) I get a programming failed message - the done pin failed to go high. I have tried a few different options in Bitgen with no success.
Also, the Xilinx ISE 'development systems reference guide' and the Xilinx answers database seem to conflict on the correct use of ngo/ngd files in the modular flow. i.e.
Development Systems Reference Guide, Modular Design Section, Top of Page 93 (PDF version)“Note: ngdbuild produces two files, design_name.ngd and design_name.ngo. The design_name.ngo file is used during subsequent Modular Design steps, while design_name.ngd is not.”
Xilinx Answer Record # 17058 6.1i Modular Design
So could the fact a am using the NGC netlist produced by ngdbuild instead of the ngo file prescribed by the Development Systems Ref Guide be causing this problem??
Please Help (Its nearly Christmas!)
Ian Colwill, University Of Sussex, UK