Hi
I wanted to sythesize a simple PRNG which is implemented as a LFSR. However, the problem is that when I debug the implemnetation on the chip I always get the same random value which are the last two bits of the tmp varible. So in my case its always 01. Can anyone tell me what I am missing? Because in simulation it works. The strange thing is that ISE 10.1 tells me XST:647: INPUT is never used. This port will be preserved abd left unconnected if it belongs to a top-level block. But I have surely connected the clk and also need it in the process for the PRNG?
entity Testbench is port( clk : in std_logic; dbg_R0 : inout std_logic; dbg_R1 : inout std_logic ); end Testbench;
architecture Behavior of Testbench is
component PRNG is port ( clk : in std_logic; R0 : out std_logic; R1 : out std_logic ); end component;
begin
--LEFT OUT SOME CODE FOR CHIPSCOPE DEGGUGING
ARCH_PRNG:PRNG port map( clk => clk, R0 => dbg_R0, R1 => dbg_R1 );
end architecture Behavior;
entity PRNG is port ( clk : in std_logic; R0 : out std_logic; R1 : out std_logic ); end PRNG;
architecture Behavior of PRNG is
begin process(clk) variable temp : std_logic_vector(7 downto 0) := B"01110101"; begin temp := (temp(1) xor temp(0)) & temp(7 downto 1); R0