Question: size of Stratix??

I ran the testbench as shown below and even though it seems to be a simple piece of code ,I keep getting errors for the syntax particularly opening files and closing them for reading or writing. I am using 3.1i Foundation Xilinx with Synopsys synthesis tools.Apparently the textio package is for simulation only and was advised to use "synthesis on/off"

The code is as follows library ieee; use ieee.std_logic_1164.all; library ieee; USE IEEE.STD_LOGIC_TEXTIO.ALL; use std.textio.all entity testbench is generic(         vwidth : INTEGER := 8); end testbench; architecture TB_ARCHITECTURE of testbench is component window_9 generic( vwidth : INTEGER := 8  ); port(         Clk: in STD_LOGIC;         RSTn: in STD_LOGIC;         D: in std_logic_vector (vwidth-1 downto 0);         w11: out std_logic_vector(vwidth-1 downto 0);         w12: out std_logic_vector(vwidth-1 downto 0);         w13: out std_logic_vector(vwidth-1 downto 0);         w21: out std_logic_vector(vwidth-1 downto 0);         w22: out std_logic_vector(vwidth-1 downto 0);         w23: out std_logic_vector(vwidth-1 downto 0);         w31: out std_logic_vector(vwidth-1 downto 0);         w32: out std_logic_vector(vwidth-1 downto 0);         w33: out std_logic_vector(vwidth-1 downto 0);         DV: out STD_LOGIC     ); end component; signal Clk: STD_LOGIC;  signal RSTn: STD_LOGIC; signal D: std_logic_vector(vwidth-1 downto 0); signal w11: std_logic_vector(vwidth-1 downto 0);  signal w12: std_logic_vector(vwidth-1 downto 0);  signal w13: std_logic_vector(vwidth-1 downto 0); signal w21: std_logic_vector(vwidth-1 downto 0); signal w22: std_logic_vector(vwidth-1 downto 0);  signal w23: std_logic_vector(vwidth-1 downto 0); signal w31: std_logic_vector(vwidth-1 downto 0); signal w32: std_logic_vector(vwidth-1 downto 0);  signal w33: std_logic_vector(vwidth-1 downto 0); signal DV: STD_LOGIC; begin UUT : window_9       port map      (         Clk=>Clk,         RSTn=>RSTn,         D=>D,         w11=>w11,         w12=>w12,         w13=>w13,         w21=>w21,         w22=>w22,         w23=>w23,         w31=>w31,         w32=>w32,         w33=>w33,         DV=>DV ); read_from_file: process(Clk) variable indata_line: line; variable indata: integer; file input_data_file: text open read_mode is "lena.bin";

--file input_data_file: text is in "A:/lena.bin"; begin if rising_edge(Clk) then readline(input_data_file,indata_line); read(indata_line,indata); D <= conv_std_logic_vector(indata,8); if endfile(input_data_file) then report "end of file -- looping back to start of file"; file_close(input_data_file);

--return;

--file input_data_file: text is in "A:/lena.bin"; file_open(input_data_file,"lena.bin"); end if; end if; end process; write_to_file: process(Clk) variable outdata_line: line; variable outdata: integer:=0; file output_data_file: text open write_mode is "vhdl_output.bin";

--file output_data_file:text is out "vhdl_output.bin"; begin if rising_edge(Clk) then outdata := CONV_INTEGER(unsigned(w11)); if DV = '1' then write(outdata_line,outdata); writeline(output_data_file,outdata_line); end if; end if; end process; clock_gen: process begin Clk <= '0'; wait for 5 ns; Clk <= '1'; wait for 5 ns; end process; reset_gen: process begin RSTn <= '0'; wait for 10 ns; RSTn <= '1'; wait; end process; end TB_ARCHITECTURE;

--synopsys translate_off configuration cfg_TESTBENCH_WINDOW9 of testbench is