Hi , I want to use the following component instantiation in my VHDL testbench:
entity tb_test is end tb_test;
architecture testbench of tb_test is
component test port ( Reset : in std_logic; Clk : in std_logic; Bidir_data : inout std_logic_vector(7 downto 0); Dir : in std_logic; Nxt : in std_logic; Stp : out std_logic ... ); end component;
signal t_Reset : std_logic; signal t_Clk : std_logic; signal t_Bidir_data : std_logic; signal t_Dir : std_logic; signal t_Nxt : std_logic; signal t_Stp : std_logic; .=2E.
signal t_tx_data : std_logic_vector(7 downto 0) signal t_drive_tx_data : std_logic;
signal t_rx_data : std_logic_vector(7 downto 0);
begin
uut : test port map ( Reset =3D> t_Reset, Clk =3D> t_Clk, Bidir_data =3D> t_Bidir_data, Dir =3D> t_Dir, Nxt =3D> t_Nxt, Stp =3D> t_Stp );
t_Bidir_data 'Z'); t_rx_data '0');
process begin -- Generate t_tx_data, t_drive_tx_data -- in this process end process;
end testbench;
My question : In the port map Bidir_data =3D> t_Bidir_data
an INOUT port of the unit under test is connected to a signal within the testbench.
Will the Tristate Description shown work ? (Which "direction does "t_Bidir_data" have ?) The testbench "t_tx_data" generation takes over the tristate bus master role.
Thank you for your help
Rgds Andr=E9