about "tri-states data bus" problem Ñ¡Ïî

my module is as follows:

entity tri_state_bus is Port ( data : inout STD_LOGIC_VECTOR (15 downto 0); cs : in STD_LOGIC; rd : in STD_LOGIC; we : in STD_LOGIC; clk: in STD_LOGIC; din : in STD_LOGIC_VECTOR (15 downto 0); dout : out STD_LOGIC_VECTOR (15 downto 0)); end tri_state_bus;

architecture dbus of tri_state_bus is begin process(clk) begin if(clk'event and clk='1') then if(cs='1') then data'Z'); elsif(rd='0') then data