I?m wondering. I wrote the following VHDL-code (this is only an example, not something usefull):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_test is
Port ( clk : in std_logic;
cnt : out std_logic_vector(7 downto 0));
end counter_test;
architecture Behavioral of counter_test is
signal counter_intern : std_logic_vector (23 downto 0) := (others =>
'0');
begin
process(clk)
begin
if rising_edge(clk) then
counter_intern
[...]
Please consider migrating to NUMERIC_STD instead of these old and poorly-standardised packages.
So you have an 8-bit output....
and a 24-bit internal counter...
[snip standard counter process] [etc, etc]
Because the synthesis tool has correctly detected that you make no use of its upper 16 bits, and has optimised them away. If you had instead picked the TOP eight bits of the counter...
cnt
You must admit though that the warning message is not very clear.Most compilers at least say something about removing redundant logic.
Thank you :-)
I tried this
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_test is
Port ( clk : in std_logic;
cnt : out std_logic_vector(7 downto 0);
extra : out std_logic);
end counter_test;
architecture Behavioral of counter_test is
signal counter_intern : std_logic_vector (23 downto 0) := (others =>
'0');
begin
process(clk, counter_intern)
begin
if rising_edge(clk) then
counter_intern >I'm wondering. I wrote the following VHDL-code (this is
Have something to add? Share your thoughts — no account required.
Ask the community — no account required