I?m wondering. I wrote the following VHDL-code (this is only an example, not something usefull):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_test is
Port ( clk : in std_logic;
cnt : out std_logic_vector(7 downto 0));
end counter_test;
architecture Behavioral of counter_test is
signal counter_intern : std_logic_vector (23 downto 0) := (others =>
'0');
begin
process(clk)
begin
if rising_edge(clk) then
counter_intern