Hi,
I'm confused over two days for the sollution of the next problem:
environment: software : WP8.1.03i & WP8.2.01i (tried with both) HW: XC3S400PQG208
I have a board which requires some clock forwarding. Input and output locations are constrained, input clock located at P76 and output located at P165. The problem is with the forwarding. I've tried with DCM, or a simple
out
Aurash,
Now changes the situation, but I stand with incomprehension. Now, the clock are forwarded, but and significantly but, synchronous upcounter isn't work. The design & report files attached below.
-------------- c.vhd --------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all;
entity c is Port ( clk : in STD_LOGIC; sys_clk_out: out std_logic; q : out STD_LOGIC ); end c;
architecture Behavioral of c is signal aaaa : std_logic_vector(6 downto 0); signal i_clk: std_logic; port (I: in STD_LOGIC; O: out STD_LOGIC); end component; begin internalclock: bufg port map(clk,i_clk); process(i_clk) ----this counter is not work, why???? begin if rising_edge(i_clk) then aaaa Reading design: c.prj
TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT
=========================================================================
---- Source Parameters Input File Name : "c.prj" Input Format : mixed Ignore Synthesis Constraint File : NO
---- Target Parameters Output File Name : "c" Output Format : NGC Target Device : xc3s400-4-pq208
---- Source Options Top Module Name : c Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No
---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Slice Packing : YES Pack IO Registers into IOBs : auto Equivalent register Removal : YES
---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5
---- Other Options lso : c.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes
=========================================================================
=========================================================================
=========================================================================
Building hierarchy successfully finished.
=========================================================================
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit . Related source file is "C:/XilinxProjects/Dummy1/c.vhd". Found 7-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized.
========================================================================= HDL Synthesis Report
Macro Statistics # Counters : 1 7-bit up counter : 1
=========================================================================
=========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx.
========================================================================= Advanced HDL Synthesis Report
Macro Statistics # Counters : 1 7-bit up counter : 1
=========================================================================
=========================================================================
Optimizing unit ...
Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block c, actual ratio is 0.
Final Macro Processing ...
========================================================================= Final Register Report
Macro Statistics # Registers : 7 Flip-Flops : 7
=========================================================================
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
Design Statistics # IOs : 3
Cell Usage : # BELS : 8 # LUT2 : 2 # LUT3 : 2 # LUT4 : 2 # LUT4_D : 1 # VCC : 1 # FlipFlops/Latches : 7 # FD : 6 # FDR : 1 # Clock Buffers : 1 # BUFG : 1 # IO Buffers : 3 # IBUFG : 1 # OBUF : 2 =========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 4 out of 3584 0% Number of Slice Flip Flops: 7 out of 7168 0% Number of 4 input LUTs: 7 out of 7168 0% Number of IOs: 3 Number of bonded IOBs: 3 out of 141 2% Number of GCLKs: 1 out of 8 12%
========================================================================= TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+ clk | IBUFG+BUFG | 7 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
---------------------------------------- No asynchronous control signals found in this design
Timing Summary:
--------------- Speed Grade: -4
Minimum period: 4.186ns (Maximum Frequency: 238.892MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 7.241ns Maximum combinational path delay: 7.743ns
Timing Detail:
-------------- All values displayed in nanoseconds (ns)
========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 4.186ns (frequency: 238.892MHz) Total number of paths / destination ports: 28 / 7
------------------------------------------------------------------------- Delay: 4.186ns (Levels of Logic = 2) Source: aaaa_3 (FF) Destination: aaaa_5 (FF) Source Clock: clk rising Destination Clock: clk rising
Data Path: aaaa_3 to aaaa_5 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.720 1.216 aaaa_3 (aaaa_3) LUT4_D:I0->O 2 0.551 0.945 Mcount_aaaa_cy11 (Mcount_aaaa_cy) LUT3:I2->O 1 0.551 0.000 Mcount_aaaa_xor11 (Result) FD:D 0.203 aaaa_5 ---------------------------------------- Total 4.186ns (2.025ns logic, 2.161ns route) (48.4% logic, 51.6% route)
========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------- Offset: 7.241ns (Levels of Logic = 1) Source: aaaa_6 (FF) Destination: q (PAD) Source Clock: clk rising
Data Path: aaaa_6 to q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.720 0.877 aaaa_6 (aaaa_6) OBUF:I->O 5.644 q_OBUF (q) ---------------------------------------- Total 7.241ns (6.364ns logic, 0.877ns route) (87.9% logic, 12.1% route)
========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------- Delay: 7.743ns (Levels of Logic = 2) Source: clk (PAD) Destination: sys_clk_out (PAD)
Data Path: clk to sys_clk_out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUFG:I->O 2 1.222 0.877 clk_IBUFG (sys_clk_out_OBUF) OBUF:I->O 5.644 sys_clk_out_OBUF (sys_clk_out) ---------------------------------------- Total 7.743ns (6.866ns logic, 0.877ns route) (88.7% logic, 11.3% route)
========================================================================= CPU : 12.40 / 13.98 s | Elapsed : 13.00 / 14.00 s
-->
Total memory usage is 137084 kilobytes
Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered)
-------------------END OF SYNTHESIZE REPORT------------------------
-------------------TRANSLATE REPORT--------------------------------- Release 8.2.01i ngdbuild I.32 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\bin\nt\ngdbuild.exe -ise C:/XilinxProjects/Dummy1/Dummy1.ise -intstyle ise -dd _ngo -nt timestamp -uc c.ucf -p xc3s400-pq208-4 c.ngc c.ngd
Reading NGO file 'C:/XilinxProjects/Dummy1/c.ngc' ...
Applying constraints in "c.ucf" to the design...
Checking timing specifications ... Checking Partitions ... Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0
Total memory usage is 65956 kilobytes
Writing NGD file "c.ngd" ...
Writing NGDBUILD log file "c.bld"...
--------------------END OF TRANSLATION REPORT-----------------
-------------------MAP REPORT---------------------------------------- elease 8.2.01i Map I.32 Xilinx Mapping Report File for Design 'c'
Design Information
------------------ Command Line : C:\Xilinx\bin\nt\map.exe -ise C:/XilinxProjects/Dummy1/Dummy1.ise -intstyle ise -p xc3s400-pq208-4
-cm balanced -detail -ignore_keep_hierarchy -pr b -k 4 -c 100 -bp -o c_map.ncd c.ngd c.pcf Target Device : xc3s400 Target Package : pq208 Target Speed : -4 Mapper Version : spartan3 -- $Revision: 1.34.32.1 $ Mapped Date : Wed Aug 09 16:00:49 2006
Design Summary
-------------- Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Flip Flops: 7 out of 7,168 1% Number of 4 input LUTs: 7 out of 7,168 1% Logic Distribution: Number of occupied Slices: 5 out of
3,584 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 7 out of 7,168 1% Number of bonded IOBs: 3 out of 141 2% Number of GCLKs: 1 out of 8 12%Total equivalent gate count for design: 101 Additional JTAG gate count for IOBs: 144 Peak Memory Usage: 138 MB
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing.
Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.
Table of Contents
----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Modular Design Summary Section 11 - Timing Report Section 12 - Configuration String Information
Section 1 - Errors
------------------
Section 2 - Warnings
-------------------- WARNING:LIT:243 - Logical network N9 has no load.
Section 3 - Informational
------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "internalclock" (output signal=i_clk) INFO:MapLib:331 - Block RAM optimization summary: INFO:MapLib:333 - No optimization performed
Section 4 - Removed Logic Summary
--------------------------------- 1 block(s) removed 1 block(s) optimized away 1 signal(s) removed 1 Block(s) redundant
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge).
The signal "N9" is loadless and has been removed. Loadless block "XST_GND" (ZERO) removed.
Optimized Block(s): TYPE BLOCK VCC XST_VCC
Redundant Block(s): TYPE BLOCK LOCALBUF Mcount_aaaa_cy11/LUT4_D_BUF
Section 6 - IOB Properties
--------------------------
+------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay | +------------------------------------------------------------------------------------------------------------------------+ | clk | IOB | INPUT | LVCMOS33 | | | | | | | q | IOB | OUTPUT | LVCMOS33 | 12 | FAST | | | | | sys_clk_out | IOB | OUTPUT | LVCMOS33 | 12 | FAST | | | | +------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------ Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
----------------------------------- Modular Design not used for this design.
Section 11 - Timing Report
-------------------------- This design was not run using timing mode.
Section 12 - Configuration String Details
----------------------------------------- BUFGMUX "internalclock": Configuration String is: "DISABLE_ATTR:LOW I0_USED:0 SINV:S_B"
-----------------END OF MAP REPORT ------------------------------
------------------PAR REPORT-------------------------------------- Release 8.2.01i par I.32 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
JOZSEF:: Wed Aug 09 16:00:57 2006
par -w -intstyle ise -ol std -t 1 c_map.ncd c.ncd c.pcf
Constraints file: c.pcf. Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx. "c" is an NCD, version 3.1, device xc3s400, package pq208, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to
85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.39 2006-06-02".
Device Utilization Summary:
Number of BUFGMUXs 1 out of 8 12% Number of External IOBs 3 out of 141 2% Number of LOCed IOBs 3 out of 3 100%
Number of Slices 5 out of 3584 1% Number of SLICEMs 0 out of 1792 0%
Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard
Starting Placer
Phase 1.1 Phase 1.1 (Checksum:98969a) REAL time: 4 secs
Phase 2.7 Phase 2.7 (Checksum:1312cfe) REAL time: 5 secs
Phase 3.31 Phase 3.31 (Checksum:1c9c37d) REAL time: 5 secs
Phase 4.2 .
Phase 4.2 (Checksum:26259fc) REAL time: 8 secs
Phase 5.8 . . . . . Phase 5.8 (Checksum:98c4fb) REAL time: 8 secs
Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 8 secs
Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 8 secs
Phase 8.5 Phase 8.5 (Checksum:4c4b3f8) REAL time: 8 secs
Writing design to file c.ncd
Total REAL time to Placer completion: 8 secs Total CPU time to Placer completion: 6 secs
Starting Router
Phase 1: 33 unrouted; REAL time: 8 secs
Phase 2: 27 unrouted; REAL time: 8 secs
Phase 3: 6 unrouted; REAL time: 9 secs
Phase 4: 6 unrouted; (197) REAL time: 9 secs
Phase 5: 10 unrouted; (0) REAL time: 9 secs
Phase 6: 0 unrouted; (0) REAL time: 9 secs
Phase 7: 0 unrouted; (0) REAL time: 9 secs
Total REAL time to Router completion: 9 secs Total CPU time to Router completion: 6 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
************************** Generating Clock Report **************************+---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ | i_clk | BUFGMUX2| No | 5 | 0.000 | 1.034 | +---------------------+--------------+------+------+------------+-------------+
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 0.772 The MAXIMUM PIN DELAY IS: 4.295 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 1.116
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >=
5.00 --------- --------- --------- --------- ------------------ 24 6 0 0 1
0Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors
------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net i_c | N/A | 2.842ns |
2 | N/A | N/A lk | | | | |------------------------------------------------------------------------------------------------------
All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 10 secs Total CPU time to PAR completion: 7 secs
Peak Memory Usage: 126 MB
Placement: Completed - No errors found. Routing: Completed - No errors found.
Number of error messages: 0 Number of warning messages: 0 Number of info messages: 1
Writing design to file c.ncd
PAR done!
---------------------END OF PAR REPORT---------------------------
Aurelian Lazarut wrote:
oops, c.vhd incorrect in my last post.
the correct c.vhd is:
---------- c.vhd ------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all;
entity c is Port ( clk : in STD_LOGIC; sys_clk_out: out std_logic; q : out STD_LOGIC ); end c;
architecture Behavioral of c is signal aaaa : std_logic_vector(6 downto 0); signal i_clk: std_logic; component BUFG port (I: in STD_LOGIC; O: out STD_LOGIC); end component; begin internalclock: bufg port map(clk,i_clk); process(i_clk) begin if rising_edge(i_clk) then aaaa
Part of the component declaration is missing here
The default port order of a BUFG is BUFG (O, I), so you either need to do explicit assignment or swap the clk and i_clk in the above.
You've got no clock!
Additionally In your original post you had out
ok, I have tried your advice, but not work...
Replaced, the original
internalclock: bufg port map(clk,i_clk);
with named pipes :
internalclock: bufg port map(i=>clk,o=>i_clk);
and not work....
and the original vesions, where I wrote out > -------------- c.vhd ---------------------------
I've run your code through a simulator just to make sure I haven't overlooked another bug. The counter should work. So, at this point I think you should look closer at your q pin assignment. Make sure it is actually soldered, not shorted, not connected to something else, etc...
/Mikhail
I'm maybe sure, this is not the hardware problem, several tests are confirmed this (for example, tested on two boards & other pins). Except if the Spartan is faulty, but other operation modes works faulty in these situation too.
Now the problem seems like syncronous network isn't work, or very faulty. I've seen the async clock forward works, but the counter isn't too...
MM wrote:
I am pretty sure, IT IS a hardware problem.
Very unlikely.
What other modes and what situations are you referring to?
What's the clock frequency? Is the board well designed and manufactured or is it a wire strapped prototype?
/Mikhail
Clock frequency tested at 24MHz, 1MHz and approx 5 Hz (with pushbutton&smitt-trigger). these frequencies failed all... PCB is manufactured as a zero series proto board.
MM wrote:
What's the FPGA's package? Is it a BGA? Can you inspect connections?
/Mikhail
Have you tried a different pin? Have you checked all the FPGA voltages?
/Mikhail
Yes, I've tried different pin, but nothing. All supply voltage is in the operating ranges. In this case, there are two boards which shows these simptoms... :S I've taken a look on PAR simulation modell, but it seems to be correct. Simulation is not equal with real physic world as I've observed in some cases. But a simple counter isn't work in real world, and works on simulation? This is my great challange to solve... now.
Jozsef
MM wrote:
Check the the PAD report. Is the signal really routed to the pin that you specified in the UCF? Are all pins using the correct logic family?
Kolja Sulimma
Jozsef schrieb:
I would check (at least) two things,
Kolja Sulimma wrote:
But beware of in slave select-map mode, when DONE really means "not quite done yet" or "you're almost done". By default, CCLK has to be strobed several more times after DONE goes high.
Have fun,
Marc
So, the secret seems to be solved. The problem is based on serial slave configuration routines. Via JTAG, the FPGA runs correctly, but same configuration stream on serial slave cannot. And I read many documentation PDFs, PPTs, HTML sites for the sollution. Now, I got a little success, now I'm passed the problem to microcontroller programmer group. About the problem: only one CCLK clock period sended to fpga after DONE pin rising to high, other documents tells this clock period must be three cycles after DONE rising high (XAPP098): one to IOs activate, one to GSR release and the last cycle to begin user operation.
now I'm waiting for the programmers group response with a correct firmware of MCU.
Thank you for the powerfull help!
Best regards Jozsef
Marc Randolph wrote:
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