Aurash,
Now changes the situation, but I stand with incomprehension. Now, the clock are forwarded, but and significantly but, synchronous upcounter isn't work. The design & report files attached below.
-------------- c.vhd --------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all;
entity c is Port ( clk : in STD_LOGIC; sys_clk_out: out std_logic; q : out STD_LOGIC ); end c;
architecture Behavioral of c is signal aaaa : std_logic_vector(6 downto 0); signal i_clk: std_logic; port (I: in STD_LOGIC; O: out STD_LOGIC); end component; begin internalclock: bufg port map(clk,i_clk); process(i_clk) ----this counter is not work, why???? begin if rising_edge(i_clk) then aaaa Reading design: c.prj
TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT
=========================================================================
- Synthesis Options Summary
- =========================================================================
---- Source Parameters Input File Name : "c.prj" Input Format : mixed Ignore Synthesis Constraint File : NO
---- Target Parameters Output File Name : "c" Output Format : NGC Target Device : xc3s400-4-pq208
---- Source Options Top Module Name : c Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No
---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Slice Packing : YES Pack IO Registers into IOBs : auto Equivalent register Removal : YES
---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5
---- Other Options lso : c.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes
=========================================================================
=========================================================================
- =========================================================================
Compiling vhdl file "C:/XilinxProjects/Dummy1/c.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled.
=========================================================================
- Design Hierarchy Analysis
- =========================================================================
Analyzing hierarchy for entity in library (architecture ).
Building hierarchy successfully finished.
=========================================================================
- =========================================================================
Analyzing Entity in library (Architecture ). WARNING:Xst:2211 - "C:/XilinxProjects/Dummy1/c.vhd" line 58: Instantiating black box module . Entity analyzed. Unit generated.
=========================================================================
- =========================================================================
Performing bidirectional port resolution...
Synthesizing Unit . Related source file is "C:/XilinxProjects/Dummy1/c.vhd". Found 7-bit up counter for signal . Summary: inferred 1 Counter(s). Unit synthesized.
========================================================================= HDL Synthesis Report
Macro Statistics # Counters : 1 7-bit up counter : 1
=========================================================================
=========================================================================
- =========================================================================
Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx.
========================================================================= Advanced HDL Synthesis Report
Macro Statistics # Counters : 1 7-bit up counter : 1
=========================================================================
=========================================================================
- =========================================================================
Optimizing unit ...
Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block c, actual ratio is 0.
Final Macro Processing ...
========================================================================= Final Register Report
Macro Statistics # Registers : 7 Flip-Flops : 7
=========================================================================
=========================================================================
- =========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
- =========================================================================
Final Results RTL Top Level Output File Name : c.ngr Top Level Output File Name : c Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO
Design Statistics # IOs : 3
Cell Usage : # BELS : 8 # LUT2 : 2 # LUT3 : 2 # LUT4 : 2 # LUT4_D : 1 # VCC : 1 # FlipFlops/Latches : 7 # FD : 6 # FDR : 1 # Clock Buffers : 1 # BUFG : 1 # IO Buffers : 3 # IBUFG : 1 # OBUF : 2 =========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 4 out of 3584 0% Number of Slice Flip Flops: 7 out of 7168 0% Number of 4 input LUTs: 7 out of 7168 0% Number of IOs: 3 Number of bonded IOBs: 3 out of 141 2% Number of GCLKs: 1 out of 8 12%
========================================================================= TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+ clk | IBUFG+BUFG | 7 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
---------------------------------------- No asynchronous control signals found in this design
Timing Summary:
--------------- Speed Grade: -4
Minimum period: 4.186ns (Maximum Frequency: 238.892MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 7.241ns Maximum combinational path delay: 7.743ns
Timing Detail:
-------------- All values displayed in nanoseconds (ns)
========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 4.186ns (frequency: 238.892MHz) Total number of paths / destination ports: 28 / 7
------------------------------------------------------------------------- Delay: 4.186ns (Levels of Logic = 2) Source: aaaa_3 (FF) Destination: aaaa_5 (FF) Source Clock: clk rising Destination Clock: clk rising
Data Path: aaaa_3 to aaaa_5 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.720 1.216 aaaa_3 (aaaa_3) LUT4_D:I0->O 2 0.551 0.945 Mcount_aaaa_cy11 (Mcount_aaaa_cy) LUT3:I2->O 1 0.551 0.000 Mcount_aaaa_xor11 (Result) FD:D 0.203 aaaa_5 ---------------------------------------- Total 4.186ns (2.025ns logic, 2.161ns route) (48.4% logic, 51.6% route)
========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------- Offset: 7.241ns (Levels of Logic = 1) Source: aaaa_6 (FF) Destination: q (PAD) Source Clock: clk rising
Data Path: aaaa_6 to q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.720 0.877 aaaa_6 (aaaa_6) OBUF:I->O 5.644 q_OBUF (q) ---------------------------------------- Total 7.241ns (6.364ns logic, 0.877ns route) (87.9% logic, 12.1% route)
========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------- Delay: 7.743ns (Levels of Logic = 2) Source: clk (PAD) Destination: sys_clk_out (PAD)
Data Path: clk to sys_clk_out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUFG:I->O 2 1.222 0.877 clk_IBUFG (sys_clk_out_OBUF) OBUF:I->O 5.644 sys_clk_out_OBUF (sys_clk_out) ---------------------------------------- Total 7.743ns (6.866ns logic, 0.877ns route) (88.7% logic, 11.3% route)
========================================================================= CPU : 12.40 / 13.98 s | Elapsed : 13.00 / 14.00 s