I try to simulate the following code on ModelSim via ISE 6.3. Behavioural, Post-Translate and Post-Mapping Simulation are work. When i simulate post-place & route, the output pattern isn't correct. I use dataflow in ModelSim to trace the problem source and found a glicth before occur unknow signal. I try to decrease clock frequency. No change from previous, it has glicth before occur unknow signal. Both situation (before and after change clock frequency), occuring glicth is very near before rising edge of clock.
My environment ============== ISE 6.3 (I try on ISE 7.1 but it's incorrect) ModelSim
VHDL code of test1.vhd.
--------------- test code (start) --------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test1 is Port ( rst : in std_logic; clk : in std_logic; a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); sum : out std_logic_vector(7 downto 0); prod : out std_logic_vector(15 downto 0)); end test1;
architecture Behavioral of test1 is
begin
process (rst, clk) begin if rst='1' then sum '0'); elsif clk'event and clk='1' then sum clk, a => a, b => b, sum => sum, prod => prod );
clk_gen : PROCESS BEGIN if clk='0' then clk