post-place & route simulation of simple project problem.

I try to simulate the following code on ModelSim via ISE 6.3. Behavioural, Post-Translate and Post-Mapping Simulation are work. When i simulate post-place & route, the output pattern isn't correct. I use dataflow in ModelSim to trace the problem source and found a glicth before occur unknow signal. I try to decrease clock frequency. No change from previous, it has glicth before occur unknow signal. Both situation (before and after change clock frequency), occuring glicth is very near before rising edge of clock.

My environment ============== ISE 6.3 (I try on ISE 7.1 but it's incorrect) ModelSim

VHDL code of test1.vhd.

--------------- test code (start) --------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test1 is Port ( rst : in std_logic; clk : in std_logic; a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); sum : out std_logic_vector(7 downto 0); prod : out std_logic_vector(15 downto 0)); end test1;

architecture Behavioral of test1 is


process (rst, clk) begin if rst='1' then sum '0'); elsif clk'event and clk='1' then sum clk, a => a, b => b, sum => sum, prod => prod );

clk_gen : PROCESS BEGIN if clk='0' then clk

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Above question, i use virtex 4 as device.

Now i change device as spantan-3 and virtex II and do post-place & route simulation again. I surprise the signal patterns're correct.

I think something are incorrect. It may be post-place & route simulation vhdl file that ISE generate.

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Try this code.

signal a1, b1 : std_logic_vector(7 downto 0); signal sum1 : std_logic_vector(7 downto 0); signal prod1 : std_logic_vector(15 downto 0); > begin >

I think the main problem is here. You were voilating setup and hold times. Changing the data at the falling edge of the clock should slove the problem for your older code too. wrote:

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Results from behavioural, post-translation and post-map simulation are correct. I think the main problem isn't above code but something after place & route process.

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