Witam
W jaki sposób mo¿na podczas symulacji uk³adu (Xuilinx ISE WebPack-ModelSim XE) obserwowaæ sygna³y wewnêtrzne (nie wyprowadzone na port). Poni¿ej przedstawiam projekt licznika z wyprowadzonym tylko najstarszym bitem. W jaki sposób ¶ledziæ wszystkie bity licznika, czy konieczne jest pod³±czenie ich do portu?
Jarek
-----test.vhd library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Test is Port ( clock: in std_logic; -- system clock (25 MHz) resetn: in std_logic; -- active low reset c_out: out std_logic); end Test;
architecture Behavioral of Test is
signal counter: std_logic_vector(3 downto 0); begin
COUNT: process (clock, resetn) begin if (resetn = '0') then counter <= (others => '0'); elsif (clock'event and clock = '1') then counter <= counter + 1; end if; end process;
c_out <= counter(3);
end Behavioral;
--------------Program do symulacji
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;
ENTITY testbench IS constant Period : time := 40 ns; -- 25 MHz System Clock END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT test PORT( clock : IN std_logic; resetn : IN std_logic; c_out : OUT std_logic ); END COMPONENT;
SIGNAL clock : std_logic := '0'; SIGNAL resetn : std_logic; SIGNAL c_out : std_logic;
BEGIN
uut: test PORT MAP( clock => clock, resetn => resetn, c_out => c_out );
clock <= not clock after (Period / 2); resetn <= '0', '1' after Period;
tb : PROCESS BEGIN wait; -- will wait forever END PROCESS;
END;