For my design, which is implemented in Virtex-4 FX12 (speed grade -10) I need to get an adjustable (in operation) clock of frequency 30 to 66 MHz with the smallest possible increments. On the board I have 100MHz oscillator from which I tried to get 400 MHz (the higher the frequency the smaller the clock adjusting increments) using EDK 8.1's DCM (CLKFX4/1). From this DCM I also power the PPC at 200MHz (CLK2X). I coupled the 400MHz clock to clock divider using rising edge as a process reference and an integer counter. This configuration does NOT work. The first problem is the frequency - EDK can compile my design if I lower the frequency to 200MHz, which is unaceptable. The other problem is a structure of my clock divider - if I make a process with rising edge detection the clock divider can only be even (clock is always divided by a factor of two!). How to build a fast dual edge (DDR) clock divider in VHDL? Is there any other way to solve my problem?