Subroutine in VHDL?

I'm trying to use a subroutine (subprogram procedure) in my testbench to (eventually) simulate processor reads and writes. When I compile and try to simulate(Xilinx ISE 6.1i and Modelsim) I get "# ERROR: testbench.vhd(34): Cannot drive signal in3 from this subprogram." Any idea why? Can it be corrected?

Thanks

Dan

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;

ENTITY testbench IS END testbench;

ARCHITECTURE behavior OF testbench IS COMPONENT tb_subroutine PORT( clk : IN std_logic; reset : IN std_logic; in1 : IN std_logic; in2 : IN std_logic; in3 : IN std_logic; out1 : OUT std_logic; out2 : OUT std_logic; out3 : OUT std_logic ); END COMPONENT;

SIGNAL clk : std_logic; SIGNAL reset : std_logic; SIGNAL in1 : std_logic; SIGNAL in2 : std_logic; SIGNAL in3 : std_logic; SIGNAL out1 : std_logic; SIGNAL out2 : std_logic; SIGNAL out3 : std_logic;

procedure set_in3 --subroutine begin in3 in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2, out3 => out3 );

-- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN reset