Xilinx Spartan 3 kit - VHDL design question

fpgawizz, I would look at the source code that represents the demo package that comes preloaded on the Spartan III starter kit. I believe the name of the file on the Xilinx Web site is : Spartan3_starter_PROM_source.zip

Within that project directory, there is a file : ./pcores/opb_7segled_v1_00_a/hdl/vhdl/userlogic.vhd

There is some OPB interface stuff in there that you are probably not interested in, but there is some stuff about how someone else thought the multiplexed 7segled should work.

I have a question for you. Why do you open new threads in this newsgroup to ask essentially the same question in a different way. I would think that it makes it more difficult for someone else to benefit from the "conversations" at a later date.

-newman

Your inputs should be std_logic. I know it's tough for beginners to cozy up with the manipulation of strings as a solution for modeling. The IEEE libraries were sort of a kludge to address some difficult questions about modeling, making VHDL one of the most verbose languages I have seen. However this is how it was done and it's best to accept it.

Your question is hard to follow. Why don't you post your code and the group can sort it out for you.

her is my code entity Display is Port ( clk : in std_logic; rst : in std_logic; d0 : in integer range 0 to 9; d1 : in integer range 0 to 9; d2 : in integer range 0 to 9; d3 : in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0); AN3 : inout std_logic; AN2 : inout std_logic; AN1 : inout std_logic; AN0 : inout std_logic); end Display;

architecture Behavioral of Display is component countdecoder is port( count: in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0)); end component;

signal count : integer range 0 to 9; signal CTR : std_logic_vector(12 downto 0); begin -- make a copy of the decoder decoder1: countdecoder port map(count => count, seven_seg => seven_seg);

Display_left_to_right: process(rst,clk) begin if rst = '1' then count

OK.

I copied your code into my machine.

And I recopied it at the end of this message with my own fomatting. I assume you are using the default library declarations that I have at the top?

Could you also send the seven_segment code so that I can run the whole thing?

Still not too clear on what you are doing with the AN inouts. Are you trying to walk a hot 0 around. Your AN3 turns on AN0 and AN0 turns on AN3. Is that what you intended?

Brad Smallridge b r a d @ a i v i s i o n . c o m

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Display is port ( clk : in std_logic; rst : in std_logic; d0 : in integer range 0 to 9; d1 : in integer range 0 to 9; d2 : in integer range 0 to 9; d3 : in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0); AN3 : inout std_logic; AN2 : inout std_logic; AN1 : inout std_logic; AN0 : inout std_logic); end Display;

architecture Behavioral of Display is

component countdecoder is port( count: in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0)); end component;

signal count : integer range 0 to 9; signal CTR : std_logic_vector(12 downto 0);

begin

-- make a copy of the decoder decoder1: countdecoder port map( count => count, seven_seg => seven_seg );

Display_left_to_right: process(rst,clk) begin if rst = '1' then count

First of all AN on the board AN is low active , so if you want to turn off the 7 segment you have to put the respective AN to 0.

Then for the counter I will not do a reset condition , i would put 1 bit less in the counter and by overflow it will come back to zero without using a comparator

And finnaly I would have use a case choice better than en elsif conditionnal

so the new code should be :

entity Display is Port ( clk : in std_logic; rst : in std_logic; d0 : in integer range 0 to 9; d1 : in integer range 0 to 9; d2 : in integer range 0 to 9; d3 : in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0); AN3 : inout std_logic; AN2 : inout std_logic; AN1 : inout std_logic; AN0 : inout std_logic); end Display;

architecture Behavioral of Display is component countdecoder is port( count: in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0)); end component;

signal count : integer range 0 to 9; signal CTR : std_logic_vector(11 downto 0); begin -- make a copy of the decoder decoder1: countdecoder port map(count => count, seven_seg => seven_seg);

Display_left_to_right: process(rst,clk) begin if rst = '1' then count AN3 seven_seg : out std_logic_vector(6 downto 0);

Like I have nothing to do at this time I have made a last, simple and optimized "display controller" that should fit to your application, it saves

40% of slice ( lol 40% sound greater than 9slices :) the refresh time is 1 cylce less than before (but over 4000cycles I think it don't really care for what you want to do) the reset became synchronous but don't really need of reset for AN and count.

here is the file:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all; entity Display is Port ( clk : in std_logic; rst : in std_logic; d0 : in integer range 0 to 9; d1 : in integer range 0 to 9; d2 : in integer range 0 to 9; d3 : in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0); AN3 : inout std_logic; AN2 : inout std_logic; AN1 : inout std_logic; AN0 : inout std_logic); end Display;

architecture Behavioral of Display is component countdecoder is port( count: in integer range 0 to 9; seven_seg : out std_logic_vector(6 downto 0)); end component;

signal count : integer range 0 to 9; signal CTR : std_logic_vector(13 downto 0); begin -- make a copy of the decoder decoder1: countdecoder port map(count => count, seven_seg => seven_seg);

Display_left_to_right: process(rst,clk) begin

if rising_edge(clk) then if rst='1' then ctr '0'); count AN3 : inout std_logic;

Thanks KCL. I used a state machine to model that part of the design. Seems like its working.ITs only a piece of a bigger part. I am trying to have this display module be one of the modules for a VHDL vending machine. Do you know any materials in the internet that can help me design this vending machine. It has the following features:

1) 5 products price - 55/60/65/70/75c 2) 3 different coin inputs -25 c/10c/5c 3) Need to display the product price and price entered via the 3 coin inputs. 4) When the value of product selected is reached, it should be dispensed and any change displayed. 5) System should reset after this and also reset if done asynchronously.

Actually what i gived to you is like a state machine and the 2 MSB of the counter are the state of the machine

"fpgawizz" a écrit dans le message de news: snipped-for-privacy@localhost.talkaboutelectronicequipment.com...