Hi,
I am designing an OPB Peripheral which has to act as a master and a slave on the OPB Bus . I am not happy with the IPIF master logic functionality provided by Xilinx . I am trying to design the master logic support myself , but the VHDL code for the Xilinx implementation is not provided in any of the directories .. Does any one have any documents / app notes , which discusses guidelines for the master logic design?
thank you venu
Just read the OPB specification (take a look at OPB bus pdf inside SDK), it is really easy to write an OPB bus master
Bets regards,
Zara
BTW: Do it more parametrized, so you may reuse it.
How easy is it to make the OPB master co-exist in EDK with other OPB peripherials? I guess one has to make at least a "signal exposer" stub with the EDK tools, so that it integrates well. Is that right?
Regards, Marc
Yes, of course, you need an MPD file that exposes the signal for the EDK. Just copy and paste the relevant parts form opb_ipif, it is fast and safe.
Regards,
Zara
Hi,
I made that OPB Bus Master-Slave Peripheral that I was enquiring about ... You were right, I dint need to use anything but the OPB manual :) . For generating the bus interface one can either check the manual or by using Create Peripheral Wizard (with the appropriate options) and copy the signals from Xilinx generated IPIF wrapper generated
I did Xilinx BFM (Bus Functional Modelling ) to test the IP. This was a really good debug tool , since any protocol violation is reported as an error message in ModelSim.
Thanks Venu
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