OPB master

Hi, did you try to make it run at a lower speed ? I encoutered the same kind of problem in a design and the problem was due to a timing issue within the IPIF which was not "clearly" reported by EDK during H/W generation. This was with version 7.1 of EDK, I don't k,ow if it is still the case in version 8.1. BTW, why don't you use the memory controler IP provided by xilinx EDK ? I use the PLB one and it works correctly on a Virtex2pro at this speed. Regards,

Manu

Guru a écrit :

Personally I don't have a high opinion of the IPIF approach. To convert from to OPB to yet another bus to use with your logic does not make logical sense to me. However the Xilinx process does have the singular advantage of generating a driver as part of the automatic process.

It would be worth considering do your own interface. If you do pick up the IBM spec it does look daunting but in reality all the FPGA implementations we have seen don't use anything like all the possible signalling. Signals to be concerned with are Abus, Dbus, Select, Xferack, timeout, retry, transfer error. Sometime you can get away without the last three. In combined master and slave modules you usually get an input version of any given the signal that come back from an "OR" array and an output version that feeds the "OR" array. When inactive signals should sit at '0' in order not to affect array output and an active output will then direct impress it's value onto the "or" output. There are gating signals for address and data but you can roll that into outputs by ensuring '0's when inactive.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development Board.

Hi Manu,

All of my test were performed at 100 MHz OPB_Clk. Lowering the the bus speed could maybe help. With ChipScope OPB/IBA I found out that IPIF Master Burst transfer is really slow - requiring at least 5 OPB_Clk cycles for ONE word (80MB/s). Since I have only one DDR on-board which contains also the PPC program lowering bus speed is out of the question (not enough bandwidth). The on-board (on Virtex4 MiniModuel) DDR is 16 bit wide which is impossible to connect to PLB for higher bandwidth. Regarding IPIF in EDK 8.1: Create/Import peripheral wizard generates the same source as in version 7.1. I tried to update the IPIF to newer version (opb_ipif_v2_06_a) but the problems remains.

Cheers, Guru

Hi John,

I thougt about doing it from scratch. It looks this is my only option. I downloaded IBM's OPB specifications and they do look daunting (about

100 pages!). In my opinion best thing to do is to implement peripheral with simple OPB master only capability (for data streaming) and DCR based control/status registers (for better response and ease of use) as suggested by IBM's CoreConnect. The only problem that bothers me is: how to start? I there any available source to start from? Otherwise It could take months just to figure out how to make a working peripheral.

Cheers, Guru

I am going on holidays right now, and have little time, but I will try to give you a little help. I have designed three OPB peripherals with slave and master interface (no DCR, as they are intended for microblaze), and they really work fine and are easy to design.

The master part must be designed as follows:

• for transactions limited to one OPB access: when needing to make a transaction, raise M_request. when MOPB_MGrant received, raise M_select and lower M_request. M_select sould be lowered after receiving xferack, errack, timeout or retry. Treat results as necessary (that is your personal option).

*for various succesive transactions Same as before, but raising M_bus_lock after MOPB_MGrant and until one-before-last transaction xferAck.

All this is easily derived form IBM "On-Chip peripheral bus", chapter

5.1 OPB Bus arbitration protocol, pages 32 to 34.

Best regards,

Zara

PS Dont hesitate to ask anything else, but I will not be available until after Easter holidays, on April 17th

I have put an example of a slave only on our website techitips page

It is a dual port ram in VHDL wired one side onto the OPB. I believe this is a working one that I grabbed but I have not checked so any problems let me know.

John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board.

Thnx John and Zara

I will take Johns VHDL as an example for building OPB master only (or master/slave) peripheral. Does anybody knows anything about DCR bus? Would I benefit a lot using it?

Cheers, Guru

DCR is for control reg, not data flow.