OPB master and slave interface for DDR SDRAM controller

Hi, I am almost new in google gruops.

I build IPIF master to control OPB DDR SDRAM controller. Using Create/Import Peripheral, I could make a IPIF master. In the folder of IPIF master, there was a example code named "user_logic." And "user_logic" has several ports, I can understand most of them. But I am not sure these 2 ports, "IP2IP_addr", "IP2BUS_addr." As long as I know, IP2IP_addr is used to choose slave that I will access. Then, how can I know address of each slave address? Can you anyone explain difference btw 2 ports?

Thank you for reading!

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