Hi everyone,
I am building a OPB peripheral. I used Create - Import Peripheral wizard from EDK 7.1 (using opb_ipif_v2_00_h). I selected Master Support, no DMA, no FIFO, 8x32 bit registers and 4 interrupts. Most of the things works fine, just Master Support gives me a lot of trouble. I have selected only one local slave register for data (on which Asyncronous FIFO will be connected) - as a source address for Master data transfer. The destination address is DDR address. I want to use burst transfer with incrementing ONLY destination address, while source address must remain constant (similar to DMA's SINC and DINC flags). Every time I use burst transfer BOTH addresses are incremented, while single beat (4 bytes) transfer works OK, but with much lower transfer speed. I modified the wizard generated "Master model functionality" in user_logic.vhd template to correct this issue, but unsucessfull. I commented the lines where addresses are incremented, but the IPIF seems to overrides my settings - addresses are incremented anyway.
Does anyone knows the solution for my problem?
Thnx, Guru