I have designed a small module usilng vhdl.I converted this module using IPIF and created an IP.Now I added this IP into my design as a master/slave module to the OPB bus.I have to inititate a transaction from my module to the OPB busi.e I want to send some data to the slave module connected to the opb bus.
One thing I have noticed is that there is no M_Dbus as output of IPIF to OPB bus.
I enable the IP2Bus_Wrreq(user logic to IPIF) high and wait for the BUS2IP_wrack signal.But nothing happens.Also there is no change in the M_request signal of the IPIF(on the OPB bus side)which is steady at 0 The following is the IPIF wrapper: port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here -- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete OPB_Clk : in std_logic; OPB_Rst : in std_logic; Sl_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); Sl_errAck : out std_logic; Sl_retry : out std_logic; Sl_toutSup : out std_logic; Sl_xferAck : out std_logic; OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1); OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1); OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); OPB_RNW : in std_logic; OPB_select : in std_logic; OPB_seqAddr : in std_logic; M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1); M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1); M_busLock : out std_logic; M_request : out std_logic; M_RNW : out std_logic; M_select : out std_logic; M_seqAddr : out std_logic; OPB_errAck : in std_logic; OPB_MGrant : in std_logic; OPB_retry : in std_logic; OPB_timeout : in std_logic; OPB_xferAck : in std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- );
What could be the problem.Is there some other signal that thas to be tken care of? Is there some other way other than IPIF that I can add my module as a master on the OPB bus. Thanks, Nitesh