Hello all, I am working on a project, in which am trying to make OV7660 camera protoboard to talk to ML300 Xilinx FPGA board.I have a general question regarding OPB bus.
Here is the set up: I am building a OPB Master peripheral which directly talks to camera (8 data, vsync, Href and Pixclk) via GPIO pins on the ML300 board. The same master peripheral talks to OPB DDR SDRAM which is a slave connected to the OPB Bus. the Master peripheral acquires the data from the camera frame after frame and stores them in the DDR(currently am overwriting the image over and over at the same address stack in DDR)
Question:: is there a limitation in terms of "clock cycles" to hold the M_Select/M_Buslock high when given OPB_Mgrant by the opb BUS. Like for example "..on a particular time once the OPB gives M_Grant a Master peripheral can hold the M_Select and M_Buslock high only for
16 clock cycles...". is there some limitation like the above?i am holding the M_Buslock and M_Select high till the transfer is complete. and it takes close to 640*480*2 pixclk to collect one frame of data from the camera to DDR SDRAM. Once the transfer is complete I do release those signals and pull M_Dbus to ground. I read through the Buslock operation given in the OPB manual by IBM and they seem to be vague on this issue.
algorithm might look like this A. Master peripheral holds M_Request high B. OPB gives OPB_Mgrant C. Master peripheral pulls M_Request low and holds M_select high to assert OPB bus and take control of the bus. and once transfer is done D. Master peripheral pulls M_Select Low
If you can help me in this regard it will be very helpful for the success of my project.