Altera Avalon Master/Slave User Defined Logic?

To all,

Is it possible to create a user defined logic that is both a master and a slave peripheral? What I want to implement is a Master peripheral which makes a request to this so-called "Master/Slave" peripheral that requests for data from the SRAM. This master peripheral first requests for an address pointer to where the data is to be retrieved from SRAM from the "Master/Slave" peripheral and this same peripheral is then responsible for fetching the information from the SRAM controller slave and then reporting the retrieved data back from the original master which made the request. Is it possible to do this, or does SOPC builder always assume a peripheral is always a slave or a master? Any pointers would be helpful

Cheers, Pino

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