Hi,
There seems to be an error in the MASTER_CNTL_STATE_MACHINE in the /pcores//hdl/vhdl/user_logic.vhd "user logic master support" generated by Xilinx EDK8.2
My IP is a Master/Slave on the OPB Bus. I have defined 4 32-bit slave registers ( slv0 , slv1 , slv2 , slv3 ) with address 30000000 to
3000000C , and am attempting to read data from memory location 20000000 to 2000000C and write it into the slave registers.
I initialised my Master Model registers with the following values: Control Register : 80 ip2ip_addr : 0x30000000 ip2bus_addr : 0x20000000 length : 0x0010 = ( attempting to transfer 16 bytes of data )
When I did the Bus Function Modelling , then only the slv0 register was being written into , none of the remaining 3 were written.
I checked the state transitions in ModelSim and noted that the "master model control state machine" was going through the following set of states:
Idle -> Last_Burst -> Check_Burst_done -> Idle
I feel the error is the following set of lines in (part of the process: MASTER_CNTL_STATE_MACHINE)
when LAST_BURST =>
if ( Bus2IP_MstLastAck = '1' ) then mst_cntl_state