Hi everyone , Can any one in brief tell me how to design a Master - Slave IP Core on the OPB - Bus ..I just need a design which could read from and write to any address that I specify ... I know how to design a slave and I was successful in it but I am not able to understand how the interaction between and Master and Slave should be because I know that we cannot design a master alone .. I m using EDK 6.3 and the ML 310 Board which has a XC2VP30 on it ..
-- Parag Beeraka