Dear friends,
I'm a novice and playing with Xilinx ISE Webpack and ModelsimXE. I have a 'TOP' Verilog module in which I have instanced 2 module: 'A' and 'B'; I have a testbench for 'TOP' and want to simulate with 'A' sinthesized and 'B' not synthesized ('B' is not synthesizable; it has for example '#...' statement). Is this possible ? How ?
Thanks and Regards
Silvano
I believe so, unless this isn't implemented in WebPack...
You can ask ISE to generate a VHDL/Verilog simulation model at most stages of implementation, i.e. post-translate, post-map, post-p&r. All you need to do is take the generated file and use it instead of your original source code. I don't know for Verilog, but the VHDL model has exactly the same entity declaration, except the GENERICs have been hard-coded, so the same testbenches can be used in each sim with only very minor modifications... The only annoyance I've had is that your signal names tend to be flattened out, and I'm not aware of any signal name equivalence file. Hope this helps,
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