Xilinx ISE 6.3 verilog simulation problem

I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...)

I have a problem simulating Post-Map Simulation Model with ISE 6.3.

I have a verilog project which consist of 2 files (a simple module an

a test bench).

My module file contain a module with ports defined as

module mux4_to_1(out, i0, i1, i2, i3, s1, s0);

And, from the testbench file, I instantiate mux4_to_1 as

mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

The sources are correct, and lower level of simulations wor

correctly. ISE generate the appropriate model files (.v, ...) an call the simulator (ModelSim). However, when I come to simulate Pos Map, ISE generate the post map simulation model, and call ModelSim but ModelSim complains about ports errors.

Looking at the generated files, I clearly see the problem. The port

are inverted.

Here are the generated models 'module' declarations:

Post-Translate verilog source:

module mux4_to_1 ( out, i0, i1, i2, i3, s0, s1 );

Post-Map verilog source:

module mux4_to_1 ( s1, s0, i3, i2, i1, i0, out );

Here, you see that the ports list is inverted. And since the module i

instantiated by passing port list by order, the ports ge miss-connected.

Anybody having this problem, and know what I can do (appart fro

specifying ports by name)?


Reply to
Big Boy
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Instead of instantiating using location use a direct connecting meaning instead of let say

andgate andgate (o,a,b);


andgate anggate (.o(o), .a(a), .b(b));

This way the order is not important any more.

The risk of using location is even higher as it can give misleading result. Assume for example that two input got swaped ...

Have fun

Reply to

Thanks berty, but I already did mentio

specifying ports by name)

That's what I'm doing now, but it's just that I'm following a tutoria

and re-typing the examples, but the examples mostly use un-name parameters

I guess though that it could be a good habit to start passin

parameters by name from the start of the learning process..

Reply to
Big Boy



I'd agree that this is a bug, but it should only show up when you use location to instantiate the top level module, not modules within your FPGA design. The "bug" is also evident in version 6.1i, but the actual behavior is not to reverse the port list, but rather to invert the order of port definitions to create the post map port list. In this case a work-around is to define your ports in the reverse order of the original port list like:

module mux4_to_1 ( out, i0, i1, i2, i3, s0, s1 );

// reverse order of port list: input s1; input s0; input i3; input i2; input i1; input i0; output out;

// code


This should cause the post-map port order to remain the same as the source module.

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