I'm still new in FPGA design, and learning Verilog, and the EDA tool (Xilinx ISE, ModelSim, ...)
I have a problem simulating Post-Map Simulation Model with ISE 6.3.
I have a verilog project which consist of 2 files (a simple module an
a test bench).
My module file contain a module with ports defined as
module mux4_to_1(out, i0, i1, i2, i3, s1, s0);
And, from the testbench file, I instantiate mux4_to_1 as
mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0);
The sources are correct, and lower level of simulations wor
correctly. ISE generate the appropriate model files (.v, ...) an call the simulator (ModelSim). However, when I come to simulate Pos Map, ISE generate the post map simulation model, and call ModelSim but ModelSim complains about ports errors.
Looking at the generated files, I clearly see the problem. The port
are inverted.
Here are the generated models 'module' declarations:
Post-Translate verilog source:
module mux4_to_1 ( out, i0, i1, i2, i3, s0, s1 );
Post-Map verilog source:
module mux4_to_1 ( s1, s0, i3, i2, i1, i0, out );
Here, you see that the ports list is inverted. And since the module i
instantiated by passing port list by order, the ports ge miss-connected.
Anybody having this problem, and know what I can do (appart fro
specifying ports by name)?
Thank