Sorry for the basic question! I' d like to know if with the ISE Webpack of Xilinx i can obtain the .vhd file of the synthesized netlist. I can view the RTL schematic double-clicking on the "View RTL schematic" option of the Synthesize tag and i can view the .vhd report of the traslate tag. The latter ( as is specified in the file ) is only for simulation purpose and haven't a one to one correspondence with the primitives and the hardware really used. Is the VHDL netlist voluntarily hidden? If not, where i can find the file? If yes, is there something that i can do to obviate it?
I'm asking that because i' d like to obtain a netlist synthesized in VHDL and try a place and route with another tool, with a standard cell library mapped on the basic gates of a XC9500 architecture.
Thanks in Advance!