floating point synthesis on Xilinx FPGAs using ISE Webpack

Hi,

you mentioned "floating point or fixed point". Don't know if this is of any use, but if you can reasonably write the algorithm in fixed point, it may be the better choice. It's' easier for some problems than for others. And, it takes some time to get used to it.

Up to 18x18 bit (typically), you get one multiplication per hardware multiplier per clock cycle. If possible, formulate your algorithm as a pipelined data path in 18 bits and even a relatively small FPGA can do a serious amount of work.

Typical fixed point code could look like this acc > 13) + c2;

where "xLSB" has 12 fractional bits (right side of the decimal point). Adding "1

What are you actually trying to build? That makes a big difference in how you do it.

In the usual case, one wants to accelerate some algorithm, which usually means a pipeline that can process some data with very high throughput. That pretty much means pipelining the floating point operation if you want floating point.

Floating point takes a lot more CLBs than fixed point, especially the floating point adder/subtracter.

-- glen

Am Freitag, 1. August 2014 18:06:30 UTC+2 schrieb vicash:

GAs that can be synthesized using the ISE Webpack toolkit. After foolishly trying to synthesize the "real" type and then researching various options I came across the following links:

ey mention using the IEEE_proposed library.

urce code for fixed and floating point math ?

nt on a Xilinx FPGA using ISE Webpack ?

Did you try out Xilinx's floating point IP-Cores ?

Regards Thorsten