xilinx design reuse netlist format

Jim, Using NGC files with ISE works perfectly for me (and i guess for everybody) The method for integrating an IP in NGC form is however not obvious :

- in VHDL : declare the entity WITHOUT architecture and instantiate it as usual : port map(clk => clk,etc...) ( in VERILOG : i dont know verilog, sorry )

- put the NGC file in the ISE project directory. Then when 'making' bitfile, you see a message saying : "reading .."

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Jerome:

Thanks for the prompt advice.

I tested the NGC file by creating another project and placing only the NGC file in that directory. I then placed 3 Verilog files - 1 is top level & the other 2 talks to the NGC'd module.

ISE 7.1 sees the hierarchy correctly but can't find the NGC'd module. So when I try to run XST or MAP or Generate Bit file, it always give an error message of Can't find module ( the NGC one ).

Verilog has no keywords for external modules. You just instantiate a module and as long as 1 of the files has that module, everything is fine.

Is there something else I'm missing ? Is there some secret ISE configuration I need to set ?

Jim

Hi again, Put the NGC file in the same directory than the source file(s) instantiating it Hope that helps