xilinx design reuse netlist format

I have a Verilog module that has been synthesized but not mapped. I would like to be able to reuse the NGC file in another design but Xilinx ISE 7 does not seem to want to read in a NGC file as one of the input files. ISE 7 also does not seem to generate a usable EDN file.

What is the recommended netlist format for IP core/design reuse ?



Reply to
James Bond
Loading thread data ...

Jim, Using NGC files with ISE works perfectly for me (and i guess for everybody) The method for integrating an IP in NGC form is however not obvious :

- in VHDL : declare the entity WITHOUT architecture and instantiate it as usual : port map(clk => clk,etc...) ( in VERILOG : i dont know verilog, sorry )

- put the NGC file in the ISE project directory. Then when 'making' bitfile, you see a message saying : "reading .."

"James Bond" a écrit dans le message de news: sEB8f.7527$ snipped-for-privacy@newssvr21.news.prodigy.com...

Reply to


Thanks for the prompt advice.

I tested the NGC file by creating another project and placing only the NGC file in that directory. I then placed 3 Verilog files - 1 is top level & the other 2 talks to the NGC'd module.

ISE 7.1 sees the hierarchy correctly but can't find the NGC'd module. So when I try to run XST or MAP or Generate Bit file, it always give an error message of Can't find module ( the NGC one ).

Verilog has no keywords for external modules. You just instantiate a module and as long as 1 of the files has that module, everything is fine.

Is there something else I'm missing ? Is there some secret ISE configuration I need to set ?


Reply to
James Bond

Hi again, Put the NGC file in the same directory than the source file(s) instantiating it Hope that helps

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.