Multiple Waits 2 Xilinx WebPack???

This is problem FPGA - Virtex and proce

proces begin if(i1='1') then go

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rules
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Incase of multiple wait statements within a single process, the wait condition must be the same for each occurance (what the error message says).

Read the "Multiple Wait Statements Descriptions" topic in the XST Users Guide. Chap 6 : VHDL Language Support > Sequential Circuits. It will give you what you need to know.

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Kunal@Xilinx

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Kunal Shenoy

Fairly simply put, this is not synthesizable VHDL. What you have here is something that is legal VHDL that can be simulated, but cannot be synthesized. Synthesis supports only a limited subset of the VHDL language, namely, VHDL (or verilog) code that maps to real hardware. Hardware consists of flip-flops, combinational logic (logic gates), and a small number of other things (tristate buffers, etc...). For VHDL code to be synthesizable, the code must describe behaviour that is consistent with these hardware elements. Your code does not...

My guess is that this is part of a testbench.

A digital circuit (i.e. one that is to be implemented in an FPGA) has inputs that come in from outside the FPGA, and outputs that are driven out of the FPGA. The "stuff" between the inputs and outputs are described using VHDL (or verilog) and then synthesized. When you want to simulate that code, it is necessary to provide signals for the inputs to the digital circuit. These signals can also be generated using VHDL. The code that generates these signals is called a testbench, and is not synthesized (since it is not part of the circuit being implemented in the FPGA), and hence does not need to restrict itself to the synthesizable subset of VHDL.

It looks like this may be some portion of such a testbench. Digital circuits usually have a "reset" input; often called "reset". To simulate such a circuit, it would be necessary to generate a pulse on the reset input, which seems to be what this code is doing.

Avrum

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Avrum

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