Hello friends, I am new to working with Xilinx tools. I have a verilog design and its pre-synthesis similation is tested. Now to verify the design, I have synthesized it using Xilinx ISE tool (using XST) to get .ngd file. a verilog netlist is generated from .ngd using ngd2ver command. I think the generated netlist uses the simprims library. i simulated (using ModelSim) the netlist using the same testbench as i used before.
vsim -L simprims_ver simprims_ver.glbl mytopdesign
But one of the signal is different. an output signal 'a_recieved' should be high for 1 clock cycle and go down, but it is high for 2 clock cycles. i didn't know any way to debug as the names of internal wires generated are completely different.
could anyone please tell if i am doing correctly and help me in debugging?
thanks kumar