I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog Primer" in order to learn not only Verilog, but how to make sure I can model designs in a way that is synthesizable.
What I have just learned is that the synthesis system (such as if I am using Xilinx ISE Webpack and it's associated synthesis tools) dictates what style must be followed, because one system might be able to synthesize model 'A' and not 'B', whereas another system might be able to synthesize 'B' and not 'A', even though models 'A' and 'B' are functionally equivalent.
Thus, this leads to the question of how to I learn about what modeling style will be synthesizable for my particular tools?
The text won't be able to teach me this, since it is just dealing with the problem in general. Obviously this must be in the tooll documentation, so I would ask:
Is there good modeling style info in Xilinx tools so that one can learn how to make synthesizable models for Xilinx tools reliably?
Finally, how to VHDL and Verilog compare in terms of *inherent* synthesizability of models, or does the same problem essentially exist for both?
Thanks for input.