MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol

Hi, I am trying to use a Memory Interface generated by MiG (Memory Interface Generator 1.72) as a symbol in a schematic based project.

CORE Generator doesn't allow me to select schematic based as a design entry when I use the Memory Interface Generator.

How can I integrate the memory interface in a schematic based design so I can used the memory for my applications?

It is for the 2 x 32 Megabytes MT46V16M16-6T:F chips on the ML402 board.

Reply to
ML402
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Generator 1.72) as a symbol in a schematic based project.

when I use the Memory Interface Generator.

used the memory for my applications?

Hi,

Generate the Memory Interface using Coregen. The easiest way will be to launch Coregen stand-alone (Start -> Run -> coregen). Create a coregen project in a new directory and generate the core. The memory interface HDL will be placed in the rtl directory. Add these files to your ISE project (make sure the files are moved to the project directory), right click the top level of the memory interface (normally tx_mem_interface_top) and select "Set as top module". After this under Design Utilities you will find Create Schematic Symbol. Set your own top level again as the top level of the project and you will find the generated schematic under Symbols -> Your project category.

Cheers Jaco

Reply to
Jaco Naude

Generator 1.72) as a symbol in a schematic based project.

when I use the Memory Interface Generator.

can used the memory for my applications?

I might have to add: This will only create a schematic symbol for the controller. You would need to do the same for your memory model.

Cheers

Reply to
Jaco Naude

Wow, thanks for the quick replies.

Yes that is the problem, I only created a symbol for the top module, mem_interface_top_main_O, so the synthesis suceeed, but errors are declared by NgdBuild since he can't find specific internal nets.

Reply to
ML402

I am starting with the easiest way to test according to ug086.pdf, I chose the DDR SDRAM design with DCM and testbench. So I'll check the ERROR and init_done signals via a LED.

Do I need to interconnect 3 symbols, interface, testbench and controller? Or are there more? I thought that making a symbol out of the top VHDL module was sufficient. Thanks.

Reply to
ML402

DDR SDRAM design with DCM and testbench. So I'll check the ERROR and init_done signals via a LED.

are there more? I thought that making a symbol out of the top VHDL module was sufficient. Thanks.

No creating a symbol out of the top level is not sufficient if you want to simulate the controller. Think about it. Only the memory controller is good if you just want to implement the design because the memory device is then in hardware and your testbench will be real signals interacting with your design and in this case you will use the trl in the without_tb folder. If you want to simulate, you need to connect the memory controller (with the rtl from the wtih_tb folder) with the memory device. MIG produces a sample top level testbench that shows this to you, note that it does not initialize the correct number of devices etc. . For example if you have a 36bit wide interface, and your memory model is only 18bits wide, you need to instantiate 2 of your 18bit models and connect them up with your 36 bit wide interface.

The error you get in NGDBuild is probably because the rest of the HDL files are not in your project (work) directory or added to the project. Add them to the project as well and the error should go away.

Cheers

Reply to
Jaco Naude

I am trying to implement the MiG design without a DCM, but with a testbench so I can see through a LED if the initialisation of the physical DDR SDRAM suceeds.

I fixed the NGDBuild errors, it was a simple hierarchy consideration in the UCF file.

Now I am getting errors concercning buffers and DCM. With a DCM, I am giving the necessary clk_0, clk_200 and the shifted clk_90 to the memory interface.

I changed the outputs of the DCM from global clock buffers to local routing and now I only have 2 errors :

ERROR:NgdBuild:455 - logical net 'N0' has multiple driver(s): pin G on block XST_GND with type GND, pin PAD on block N0 with type PAD ERROR:NgdBuild:924 - input pad net 'N0' is driving non-buffer primitives: pin G on block XST_GND with type GND

How can I locate these errors? What part of ISE do I use to get more information?

By the way, this is my first project on FPGA prototyping board, so yes I am learning all at once, hehe.

It is great to see that this forum is very active, thanks again!

Reply to
ML402

NGDBUILD done. Process "Translate" completed successfully

Now I have this error during mapping : ERROR:LIT:297 - BUFG or BUFGCTRL are the only valid components that can drive REFCLK pin of IDELAYCTRL symbol mem_interface_top_inst1/mem_interface_top_idelay_ctrl0/idelayctrl0.

Reply to
ML402

Do you have a DCM that you instantiate yourself? If you generate a controller with MIG without a DCM you still need to have your own DCM outside the controller to remove skew from your clocks. Otherwise this can give you problems later on. I would really recommend generating your MIG design with the DCM etc. taken care of already unless you are experienced enough or you run out of DCMs.

The problem that you get in MAP is because the clock that drives the REFCLK on the IDELAYCTRL is not on global routing. I would recommend that you have a look at the MIG User Guide and make sure your signals matches the signals shown in the Top-Level Block Diagrams. You will see that the clk_200 that drives the idelay_ctrl must come out of a DCM.

Hope this helps, Cheers

Reply to
naude.jaco

Yes I connect the DCM's outputs, CLK0_OUT, CLK90_OUT and CLK2X_OUT to the MiG interface's input ports clk_0, clk_90 and clk_200. My reference clock is 100 MHz SYSCLK_100MHZ on pin AE14.

You are right about the global routing, but with it I get these errors :

ERROR:NgdBuild:770 - IBUFGDS 'CLKFB_IBUFGDS_INST' and IBUFGDS 'CLKFB_IBUFGDS_INST' on net 'N0' are lined up in series. Buffers of the same direction cannot be placed in series.

So do I need to edit the VHDL of the MiG interface to remove the buffer from its DCM's input? The best solution for me is via my main schematic file, thanks.

Reply to
ML402

Would it be possible to use the same DCM for my entire design? Its CLK0_OUT would come back to its feedback input port, would drive clk_0 input of the MiG interface and be the 100 MHZ clock for my other design modules? What buffer configuration would allow that, or do I require multiple DCMs? Thanks.

Reply to
ML402

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