Hi,
I am trying to use MXE-III to simulate a design (Target V4-FX12) including a block memory core generated by Coregen (EBKMEMDP_V6_2). ModelSim DOES NOT initialize memory's value defined in generated "XXX.mif" file. Can anyone give some clues? This issue bother me 2 days. Thanks.
Alpha
Hello,
If you instantiate a memory manually, then you might not specify the valid path to MIF file. I think that when you use the memory using the instance template generated by CoreGen, there is a link to the MIF file, check if this link is valid. If it is, but you still do not get the right values, check with xilinx, i.e. you are using compiled libraries, may be there's a problem with the compiled model? Any possible limitations of this model? Cannot really think of anything else...
Vladislav
Let's assume your top level is called 'system', which is the default
EDK produce the simulation files, along with another file calle
'system_init.[v/vhd]'. That last file contain the initialization fo the memory
You need to initialize the memory with that file
Depending on if you are making verilog or vhdl target, the procedur
may be different. I don't know about VHDL, I use Verilog. Fo Verilog, you need to start simulation of 'system' (in system.v) an 'system_conf' (the main module in system_init.v) at the same time both as top-level. 'system' must be top-level in simulation too s if you have a testbench, it must run in parallel with 'system module
You do this by specifying multiple modules to the 'vsim' command i
ModelSim
Ex
vsim -t ns system_conf system testbench glb
In your testbench, you connect to 'system' as follo
-- module testbench() //top-level 'testbench' only serve to connect t top-level 'system' module test test1(.clk(system.clk), .a(system.a), .b(system.b) .y(system.y) endmodul module test(clk,a,b,y) //Put your stimulus her reg reg reg cl wire . endmodul
I would also take a look to the XCO file.
It may be corrected in 7.1, but ISE 6.3 may fail to update XCO files if they are located in a directory different from the main project. Only the local copies of the XCO (created when the IP is generated) present in the main project directory present are updated.
Hi,
I switch to single port block memory core, this time ModelSim works for given init files (X.mif). I believe it is Coregen issue. Hope Xilinx have fix in 7.1's SP3.
Alpha
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