Has anyone activated this yet?
i found this ddr controller on the xilinx website: memory interface generator (MIG). it was on demos on demand as well. it is a simple program that supposedly generates everything you need. it seems neat, hdl seems ok. though it's done on ML461 board and it gives wrong .ucf files even for ML461 itself (there is another sample code of pretty much same controller there (xapp709) so i compared it with the generated one).
can someone please help me with the pinouts here. i've figured out data and address pins (well, i think i have) and now i am left with controls.