Help on DDR SDRAM contoller generated by MIG1.5

I've been using the DDR2 interface from MIG 1.5, and the interface can be generated with or without the test bench. I just checked MIG, and it looks like you're right, it can only be generated with the testbench. In the DDR2 interface it was tedious but possible to 'unwire' the testbench and connect my own interface. The hierarchy of the DDR interface looks to be the same as the DDR2 interface, so I think that the job shouldn't be too difficult. As for doubts about the quality of the DDR code, you should do a thorough simulation. I have opened 4 or 5 webcases on the DDR2 MIG 1.4 and 1.5.

Hi Subin,

It is possible to remove the test bench. If you decide to do so, you may have to bring out the interface signals and tie them up to your application.

also, did you check the user guide? We do have the structure documented in the user guide.

You can also use the Xilinx Help desk to get answers to these questions. ( snipped-for-privacy@xilinx.com is their email address).

thanks, Nagesh

sub> Hello guys,

In the DDR2 design, the testbench is integrated into the design several levels of hierarchy down from the top. All that is exposed at the top are the signals to the SDRAM and an error signal. If you go to the main_0 hdl code, you will see that test_bench_0 and top_0 are instantiated there. You will have to find the user interface signals that pass between test_bench_0 and top_0 and route them up the hierarchy. It would have been a lot nicer if the testbench connected to the memory controller at the top of the hierarchy like a user's interface would. You will have to remove the test bench because it will drive signals that your design also has to drive.