Hello guys, Is anyone used the Mig tool to generate a DDR SDRAM controller here.i have some doubts on the code generated by mig.It include a testbench inside it.I dont need such a interface and also i want to use this as a sub block of the Full system fpga of the v4lx60 board. i am confused with structure of the code.Is it possible to use this code with out much modification such as not removing the testbench. regards subin
- posted
17 years ago