MIG for Virtex-4 DDR dimm, only 165 Hz?

Jun 19, 2007 2 Replies

Hello,



Why does Xilinx MIG controller support DDR dimm at only 165 MHz in Virtex-4 ? (175MHz in -12). I remember seeing a 200 MHz reference designs for DDR memory in a V2Pro!



Quoting from the white paper "Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generator": "For high-performance applications, pushing the limits of the memory interface bandwidth like 533 and 667 Mb/s per pin DDR2 SDRAMs, Xilinx offers the Virtex=E2=84=A2-4 and Virtex-5 FPGAs, which are capable of meeti= ng the highest bandwidth requirements of most systems today."


533? That's like 266 MHz. 200 MHz should be easy for MIG then. 165 MHz is a far cry from the marketed 266 MHz.

AR23862 answers part of this question (something about idelay jitter). Still, I feel that the MIG design should be able to extract more performance from the V4 fabric.



Side question, why can MIG acheive 220 MHz with DDR2? That's like 33% faster.



Thanks.



Patrick



ting

The controller generated by MIG tool is not efficient. There was lot of bugs in the code i generated using 1.6 version. They are not sure it's works in the higher frequency. That's why it's shown 165 as the limit. But you can make changes in the code and can try to work for higher frequency. Regards Subin

We are thinking about using the Direct-clocking part of the MIG for DDR2 (which runs at 220 MHz) as a reference and integrate this in the MIG for DDR memory. I'm assuming that the differences between DDR and DDR2 are small enough that this could work, but maybe I'm mistaken.

Hopefully with that trick we could go higher than 165 MHz (we really need 200 MHz). Does that seems like a good idea or not?

Patrick

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