FPGA & DDR-SDRAM

That would be correct in the functional sense. Only the data lines (and byte strobes, if used) would need to be separate.

However, it might be easier (from a signal integrity P.O.V.) to use separate address and control lines for each DIMM.

Regards, Allan

Hi Allan,

thanks for your immediate reply. But could you please elaborate on the pro's and con's regarding the seperate and combined data and adress lines (the last thing you mentioned in your answer)?! That would really help me in making the right decision...

Thank you very much in advance!

"Allan Herriman" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

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Download a copy of a signal integrity analysis tool such as hyperlynx and play with it for a while. It will soon become apparent that a simple "point to point" connection can be made to work at speeds up to several hundred MHz without too much pain, but things are a little harder if you have multiple loads. The signal will take longer to settle, and this will eat into your timing margin.

I assume that you will be using a clock of >= 200MHz, which means that your timing margin is probably less than 1ns.

Also, when simulating, don't forget to take the DIMM tracks into account. You care about the signal quality at the chip pins, not the DIMM pins.

Regards, Allan

Hi Allan, Good points but, playing Devil's advocate, with just one address/control bus, there's only half as many signals to worry about. Duplicating the busses, you start eating up board area, lengthening the traces, making the problem worse than if you just placed the two DIMMs right next to each other on the same short bus. So, I vote for one bus. Especially as the DDR SDRAM data sheets are full of apps notes telling you how to do it! Cheers, Syms. p.s. If you're really worried, I believe Xilinx will tell you about the trace lengths in the BGA package substrate to include in your simulations.

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I'd agree with the single address/control bus as well if the two modules are placed next to each other as are typical dual-DIMM systems. The only difference here is that the bank selects are common to both modules rather than separate and there are twice the number of byte lanes. Otherwise, all dual-DIMM issues still apply. Different clocks go to the different modules so there is 1 load per clock. A preload of the address/control bus may be helpful. Check out the Micron app notes for DDR DIMMs and you'll see the issues that need to be addressed for using two DIMMs.

If the board is too crowded with 16 bytes lanes going through 2 DIMMs (which does sound agressive) then the separate address/control for the separate modules would be helpful for DIMMs that aren't parallel.

In addition, many (all?) of the address and control signals aren't DDR (i.e. they only make one transition per clock), which allows for more settling time.

C.F. the data signals, which can make two transitions per clock.

Regards, Allan

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Hi, thanks. You already helped me alot, folks! I searched the Micron homepage but unfortunately didn't get the information (about using two DDR DIMMS at the same time) you mentioned. Would you please be so kind to send me the link or pdf?

Regards, Quinn

micron.com

-> Modules, DDR SDRAM

---> Technical Notes (tab)

Lots of good info. The "compensation" that I read about a long while ago was in TN-46-07, DDR333 Memory Design Guide for Two-DIMM Unbuffered Systems at

Happy hunting!