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MIG core generator problem

Hi,

I have one question about Memory Interface Generator. This problem I can't solve for a period of time so I decided to ask help. The thing is this. I generate my Mig core from the project. THis process pass ok. But when I want to implement my design I have problems.

First thing that bugs me is this. When I start implementation of design I am gettign messages that my core is not recogneze (that my xco file is not included or vhd or something), but this is inposible because Istart core generator form my project and it is loaded automaticly. Anyway, bacause of this ISE ask me to redesign my core so I have to do this that I can go to the next step. When I finish this, imlementation process continiues and after while I get this error

":NgdBuild:604 - logical block 'u_moj_mig' with type 'moj_mig' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'moj_mig' is not supported in target 'spartan3a'."

I want to add those files to the project but ISE tell me that ngc file is already in the project (strange).

Has nayone ever worked with this MIG core

I need any kind of help advice anythig.. Thanks in forward for your help Zoran

Reply to
Zorjak
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I ran in this kind of trouble if XST tries to compile the simulation file of a core. Have a look at the compile log, whether there a errors during compiling your core. If you have an ngc file compiling is not necessary.

Tom

--
Thomas Reinemann, Dr.-Ing.
abaxor engineering GmbH
www.abaxor.de
Reply to
Thomas Reinemann

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