DDR Simulation via MIG

Sep 06, 2007 2 Replies
M

I am looking into a MIG-generated DDR SDRAM interface and am having trouble with the simulation. I can see the interface go through the intialization sequence, but when it gets to the first dummy read to cal the IDELAY's on the data lines, the data that comes back from the RAM is all 'x' except for the least significant 16 bits. Unfortunately the comparison checks look at everything except those bits and the first check never finishes.



I have generated these files based on a known RAM DIMM...not a user RAM. And I just used all default values. I am just trying to get educated on DDR. Is there something I am missing? I followed the steps in the sim readme file.....



Thanks!



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M

The problem is in the testbench file that the MIG creates. It only instantiates and connects 1 memory IC. Thus from a module perspective, there is a lot missing. I instantiated 3 more IC's to get the thing working.

Xilinx should explicitly state that info in the readme file. I didn't pick up on it from that file or the MIG user guide..but maybe I'm dense.

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D

Hi Motty,

I checked with a MIG specialist "The readme in the sim directory does give some information on this. MIG 2.0 which is coming with IP Update #2 in October will provide testbenches and memory models specific to the option specified in MIG so this will no longer be an issue."

Thanks Duth

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