Help on simulating ddr controler generated by MIG!!

I simulate the ddr controler generated by MIG(memory interface generator). The result of behavior simulation is correct ,but there's someting wrong after synthesis. The wave is unknown after ddr sdram initialization. I affix the captured picture in this mail. I use synplify 8.2.2 to synthesis the design, and use modelsim 6.2a to simulation it.

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orthogonal
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result of behavior simulation is correct ,but there's someting wrong after synthesis. The wave is unknown after ddr sdram initialization. I affix the captured picture in this mail. I use synplify 8.2.2 to synthesis the design, and use modelsim 6.2a to simulation it.

Reply to
subint

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