How to trsiate o/p pins?

Hi, I am new to designing with FPGAs. I have an enable_output pin in my FPGA which if deasserted will make the o/p data pins(32 pins) to Hi-Z state. I would like to know how to make these o/p pins as Hi-Z by using the control input (i.e) enable_output. I using Verilog and Synplify Pro for synthesis and Xilinx ISE7.1 for PAR.

Thanks & Regards, Srini.

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It's straightforward in VHDL:

buspins 'Z');

I guess in verilog it's something like:

assign buspins = (OE) ? drive : 32'bz;

but I'm not a verilog expert.

I'm sure the Synplify help tells you all about inferring tristate pins, but I can't find it myself :-(



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Martin Thompson

To be equivalent to VHDL code it would be

assign buspins = OE ? value : 32'bz;

(parentheses are not required)

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