FPGA Verilog state machine lock up


I am using Verilog to program a Xilinx FPGA. The program is basically a state machine with at least 32 states. There is an internal counter that counts and allows the state machine to move from one state to the next. This program simulates well both pre and post synthesis and goes through all the states continuously. Once it is loaded into the FPGA it gets stuck up in one state. The solution I realised was to increment the counter value at the state where it is stuck when the state machine transitions to the next state. There is enough time between states as it is. I am not sure why this is happening. I will appreciate if I can get some tips on this issue.

Thanks Neena

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Maybe one of the inputs is not synchronized to the fpga clock.

-- Mike Treseler

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Mike Treseler

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