How to do one hot state machine in verilog for Xilinx V5 using XST

Repeat 3 times: "Google is gooood."

I am still unable to see the xst directive that telss the the xst synthesis tool that the state machine is one-hot. Is there such a thing?

Google is good.

Find "XST User Guide" (in PDF) on xilinx.com. You will find plenty of informations about XST. The same goes for "Constraints Guide" (also PDF).

(for VHDL) attribute fsm_encoding of {entity_name|signal_name}: {entity|signal} is "{auto|one-hot|compact|gray|sequential|johnson|speed1|user}"; (for Verilog) // synthesis attribute fsm_encoding [of] {module_name|signal_name} [is] {auto|one-hot|compact|gray|sequential|johnson|speed1|user};

Cheers

I do believe the xilinx tools default to 1-hot implementation if left unspecified.

This is in fact true. It's also very annoying if you don't realize this and scratch your head for days wondering why a simple state machine with a 3-bit binary encoding and 8 states can lock up...