Hi, I am using the "syn_useioff = 1" directive in my top module to pack the Input/Output registers into the IOB and synthesizing using Synplify Pro. For PAR, I am using Xilinx ISE 7.1 I would like to know how to check and see whether the input and output registers are packed in the IO blocks after PAR. Also, I am tri-stating my outputs based on a control signal by using the following syntax in verilog : out_data = 16'bz. So, I want to check whether the tri-state buffers and the output registers are placed in the same IOB. Can this be done? Some people are telling that this verilog syntax will not actually tri-state the outputs in implelementation and I have to specifically instantiate the tri-state buffers from Xilinx. Can anyone clarify me about this?
Thanks & Regards, Srini.