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Automatic I/O voltage sensing (as XILINX ParallelCable IV)

Hi all,

Sorry to ask about analog question, but it 's relative to FPGA too.

Do you know a schematic to do 'Automatic I/O voltage sensing' as XILINX does with the ParallelCable IV.

I am designing a new JTAG interface (USB), and I want to be able to drive correctly the target JTAG signals (3.3V, 2.5V, 1.8V, 1.2V).

Are there any lvttl level shifter device to do this work?

Thanks for your advice.

Laurent Gauch

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Amontec Team, Laurent Gauch
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On the recieve side, probably the best thing is to use a LVDS pair with one side for your input (maybe divided by 2 with low value resistors to be able to get the 3.3V range) and the other side biased with a PWM generated voltage to set the input threshold. The common mode range and speed of the Xilinx LVDS inputs is impressive...

Peter Wallace

Peter Wallace

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Peter Wallace

Laurent

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Stephan Buchholz

Thanks,

You confirm what I'm thinking to use.

For your info, GTL2010 is corresponding with TVC family from Texas. I will try with this !

Laurent

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Amontec Team, Laurent Gauch

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