I am using VCS compiler to do the Xilinx FPGA timing simulation. I have 16 bit state machine in one of my verilog submodule. I am able to do the timing simulation but not sure the exact proecdure in locating the internal state machine and be able to see on the waveform viewer.
Albert
My theory is that recently people are taught to never solve their problems by asking questions on the newsgroups. So they make statements and watch for responses.
There's a question here? (Besides this one, so far) _________
The VCS compiler is for timing only, right? Is your synthesizer XST? Do you have state machine optimization on or off? Have you looked at your XST technology view to see how the logic was implemented?
Chances are you need to do some spelunking in your intermediate files or the XST post-synthesis viewer. Your original state machine may now be a very different representation that what you started with in your HDL.
- John_H
John,
I have been taking hunt and pack approach in locating the internal signals of the fpga fabric - for example looking at the intermiediate files etc. I felt that there may be a better way to do this. This is why I wanted to pose this question on this forum. It just seems that if there is no direct way then that is a problem that should be fixed.
Albert
Hi Albert - [1] You might want to try bringing the state machine bits to either a port on the module, or even to external I/O signals to facilitate monitoring. Buffer with either one level, or two level of FFs so as not to exacerbate route effects on timing..
[2] I complete maybe 10 FPGA designs per year, and have not performed a timing simulation of gate level netlist in many years. RTL simulations find logic flaws ...... static timing tool ensures timing integrity of design.Good luck.
-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com wrote in message news:eea895b.-1@webx.sUN8CHnE... >I am using VCS compiler to do the Xilinx FPGA timing simulation. I have 16 >bit state machine in one of my verilog submodule. I am able to do the >timing simulation but not sure the exact proecdure in locating the internal >state machine and be able to see on the waveform viewer. > > Albert
John Retta,
I am relatively new to the FPG design. I normally use the PERIOD constraint on my synchronous designs. But I have this design where I am 5 different clock domains. Some of the clocks are derived from the fpga pll output and to the bufg. The software seems to change names of these clocks so if I specify the PERIOD contraint in the ucf file then it does not get recognized correctly - sometimes it sees no load to the clock with PERIOD constraint and sometimes the software does not see the clock.
I am not sure what will be the best wat to specify the PERIOD constraint to intenal clocks of the FPGA fabric. I wish that the Xilinx sofwtare gets smarter here and asks the end user about specifying the PERIOD constraint to "hard to reach" clocks.
Albert.
Not to worry .... we were all new to this at some point.
So to find out the names of clocks, you have to options. First is to check the .par report file. That should show you the clk domains with named clock net.
Other option is to open the constraints editor and select the .ngd file - I think that is the correct one. This tool will then display the list of named clks that you can put a constraint on. For me, I use the constraint editor to find the names of clks ( when tool has not named them in way I expect), or if I want to figure out the syntax for constraints I do not use frequently. "Feature" of constraint editor, is that it mucks with original .ucf file ... and may make this file difficult to read. Like my own formatting a little better.
Also, with regards to renaming ... if you keep your clk name same through various levels of hierarcy, clk_100mhz for instance, then the problem of which point in netlist it chose to pick out net name occurs less often.
-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc.
email : snipped-for-privacy@rtc-inc.com web :
Thanks John. I will follow your advice. I have been afraid of using the constraint editor as it overwrites the ucf file but I can keep a copy of good ucf file.
I am using Virtex5 deivce and it is way under utilized as far as the LUTs are concerned. I am hoping that I can run the fabric at 200MHz.
Albert
the fpga fabric - for example looking at the intermiediate files etc. I felt that there may be a better way to do this. This is why I wanted to pose this question on this forum. It just seems that if there is no direct way then that is a problem that should be fixed.
The synthesis tools usually have reports when logic is changed from the RTL to an "optimized" form. Since you are allowing state machine optimization, take a look at the reports that are generated by the synthesis tools. If you're in unix, you could grep on the state machine bit names and probably find a line that states the conversion happened
*and* perhaps what the new names are.Which synthesizer are you using? XST?
Insert an output signal into each state.
John,
I am using XST Synthesis tool on Linux. But we also have Synplify from Synplicity. You mentioned about doing a grep. You do this on .ncd or .ngd file?
Albert
Synplicity. You mentioned about doing a grep. You do this on .ncd or .ngd file?
I don't know the XST synthesis report files since I strictly use Synplicity tools.
The .ncd and .ngd are not report files so they would not include user-readable information.
Run XST synthesis and check what files are generated by the tool (by looking at the time stamps) and grep anything that looks like a report file.
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