Testing a Verilog design after synthesis in Xilinx ISE

Just simulate it with the same testbench you used to test the verilog design (i.e. use the post place and routed generated verilog file with back-annotated timing file (sdf file) with your testbench and you should then now how good it really works.

Salman

Hello everyone, I have a verilog design that is tested with ModelSim simulator and it works properly. I have synthesized it with Xilinx ISE Tool using XST and I want to test it(after synthesis) before I can go on with downloading the BIT file onto a Xilinx FPGA board. I could not find a way to do it. Can anyone please help me in this matter?

Thanks a lot, Kumar

ngd2ver converts an ngd file back to verilog, you can plug the gate level verilog file back into your testbench. Simulating a gate level netlist is painfully slow especially with a slow simulator like ModelSim. Unless you suspect that you've had a synthesis error there is no reason to do a gate level simulation. Even if you suspect a synthesis problem you are better off trying to narrow it down using ChipScope then trying to do a gate level simulation.