I am a newbie in Xilinx FPGA and am trying to prototype my own architecture. I tried the tutorial about stopwatch. Everything is OK.
Then I tried a simple design "3-bit counters". The behavioral model and translate model works. But the post-map model doesn't work. I don't know why?
Here I did't use DCM. I have the clk pin feed to my counter directly. Could this cause a problem?Thanks,