Hi ,I've been working on this for three days and I got lost in the se of XST warnings and errors .... I'm really lost.. In short ,what want is to design a combinational module that will interface betwee the datapath of a cpu with blockram's bidirectional datalines..th module should include an input port and outport both connected t register file's read and write ports, and a bidirectional por connected to the ram's datalines..
Target device is Spartan 3
PLZ HELP